One type of high power transistor uses a plurality of polysilicon gate fingers located in an active area of a silicon substrate. A source and drain region are formed on each side of each of the gate fingers. A channel region is located directly below the gate fingers. The gate cross section for the shortest distance between source and drain is called gate length. The dimension perpendicular to this is the finger length or the transistor gate width. For a single transistor, multiple fingers might be connected in parallel to increase the gate width. The sum of all the finger lengths is then called the gate periphery. Assuming the cross sections of all fingers are identical, the power capability of a transistor is determined by the power capability of a unit finger length multiplied by the total periphery. The number of fingers that a high power transistor can have is determined by various limitations, including for example, the size of the package in which the high power transistor must fit. Also, increasing the length of the fingers increases the gate resistance (Rg) which is another important high frequency parameter. In one high power transistor, to overcome the increase in gate resistance, a low resistivity material, for example, a metal, is run parallel to the gate fingers over the source area to form a gate bus. The gate bus periodically contacts the gate fingers to reduce the gate resistance Rg. Gate pads are placed and sized to allow a contact from the gate bus to be landed. However, lowering the gate resistance in this manner results in a higher parasitic gate-to-source capacitance (Cgs) because of the additional polysilicon gate area needed to facilitate the connection to the gate bus. The higher Cgs has an adverse effect on the performance of the transistor through an increase in the RC time constant and a change in the Cgs characteristic.
Therefore, there is a need to minimize the parasitic Cgs of the transistor while maintaining a low Rg.